Method and device for generating a clock signal that is coupled to a reference signal

ABSTRACT

In order to generate a clock signal (f T1 ) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (f T1 ) is generated from a high-frequency clock pulse (f 0 ) and the reference signal (FBAS) is digitized therewith. In addition, a second clock pulse (f T1 ) is generated from the high-frequency clock pulse (f 0 ) and the phase deviation between the first clock pulse (f T2 ) and the second clock pulse (f T1 ) is determined. The digitized sampling values of the reference signal (FBAS) at the first clock frequency (f T1 ) are converted, according to the phase deviation determined, into corresponding digitized sampling values having the second clock frequency (f T1 ) and are used as a target specification for generating the second clock pulse (f T1 ) thus coupled to the reference signal.

[0001] The invention relates to a method and a device of corresponding design to generate a clock signal which is coupled to a reference signal, wherein the invention is applicable, specifically, to generate a line-coupled or color-carrier-coupled system clock signal for a corresponding decoder of the video signal.

[0002] In most integrated circuits (ICs) for video processing, especially in the area of digital television, a so-called line-coupled or color-carrier-coupled clock signal is required which is coupled to the analog video signal (FBAS signal), and thus synchronized with this signal. In principle, two different couplings are possible here—line coupling or color carrier coupling. In the first case, the horizontal sync pulses of the video signal are used as the reference for clocking, while in the second case, the so-called color burst of the video signal is used.

[0003] Today, two different approaches are used to achieve the above-referenced coupling.

[0004] In the first approach, the system clock provided for the respective IC is re-adjusted based on the synchronization signals contained in the FBAS signal. The analog-to-digital converter normally provided to digitize the FBAS signal is operated at the same system clock.

[0005] With the second system clock, the respective system, and thus the analog-to-digital converter as well, are completely free so that the FBAS signal is sampled asynchronously by the analog-to-digital converter. A digital circuit calculates the deviation between the actual sampling frequency and the virtual sampling frequency coupled to the FBAS signal (so-called skew value), and then corrects the asynchronous sampling values of the digitized FBAS signal.

[0006] Due to the large-scale integration (“system on a chip”), it is necessary to accommodate both of the above methods on one IC since each method has advantages for specific system components. In order to use both methods simultaneously, however, the analog FBAS signal would have to be analog-to-digital-converted twice, whereby the one analog-to-digital conversion is implemented using a free-running clock, that is, with an asynchronous clock signal not coupled to the FBAS signal, while the other analog-to-digital conversion is implemented with a coupled and regulated clock signal. Due to its overall complexity, however, this approach is not feasible.

[0007] Increasingly, there are applications in which signals digitized at another location, such as FBAS signals or other signals, are already coupled with a clock. This should occur independently of the clock the digitization and received data sequence are tied to. Such applications are found, for example, in personal computers in which the system clock is generally fixed and which determine the digitization and data sequence by means of predetermined processing groups.

[0008] The goal of the invention is therefore to propose a method and a device to generate a clock signal coupled to a reference signal, wherein the above problems are solved and wherein the two above-described approaches are jointly implemented with low complexity on one IC.

[0009] This goal is achieved according to the invention by a device with the features of claim 1 or a device with the features of claim 10. The dependent claims define specific advantageous and preferred embodiments of the invention.

[0010] According to the invention, a free-running clock signal and a clock signal coupled to a reference signal are derived from one and the same (high-frequency and quartz-coupled) clock signal. The resulting pre-knowledge of the phase position of the different clock signals relative to each other may be used to calculate or convert the digitized sampling values of the analog-to-digital converter, which is operated at the free-running asynchronous clock frequency, to digitized sampling values corresponding to the coupled clock signal, which values in turn form the basis for generating or regulating the coupled clock signal.

[0011] A considerable advantage of the invention is the simple and precise obtaining of the phase position between the two clock signals by which in this case, specifically, an additional analog-to-digital converter may be dispensed with—with the result that the invention requires only a single analog-to-digital converter.

[0012] A completely digital phase-locked loop with a digitally-controlled oscillator (“digital timing oscillator,” DTO) may, for example, be used to control the coupled clock signal, with the result that analog components, which are always technology-dependent and difficult to test, are eliminated in the control circuit. Of course, other systems such as delay lines, etc., to output the coupled clock signal are also conceivable.

[0013] The conversion of the free-running clock signal of the digital sampling values with the free-running clock frequency from the analog-to-digital converter to corresponding sampling values with the coupled clock frequency may be performed by a preferably linear interpolation which is implemented on the basis of the determined phase position or phase deviation between the free-running clock signal and the coupled clock signal. For this purpose, the sampling values of the analog-to-digital converter required for interpolation are stored simultaneously with the phase value determined each time in agreement with the coupled clock signal, and fed to a corresponding interpolator.

[0014] The invention may be used preferably to generate a clock signal coupled to a television or video signal in the field of digital television. However, the invention is not restricted to this preferred application but may be utilized anywhere there is a need to generate a clock signal coupled to a reference clock signal.

[0015] The invention will be explained in greater detail with reference to the attached drawing based on a preferred embodiment, the single figure representing a simplified block diagram of a device according to the invention based on the preferred embodiment.

[0016] With integrated circuits for video processing such as those used in digital television receivers, it is often necessary to couple the internal clock signals with the received analog video signal (FBAS signal), wherein two different couplings are in principle possible, specifically, a line coupling or a color carrier coupling. In the first case, the horizontal sync pulses of the video signal are used as the reference for clock generation, while in the second case, the so-called color burst of the video signal is used. The following approach assumes that coupling with the horizontal sync pulses of the received video signal is implemented. It is self-evident, however, that the invention is also applicable to the case of color carrier coupling.

[0017] In the embodiment of the figure, the analog FBAS signal is sampled by an analog-to-digital converter 1 at a free-running clock frequency f_(T2) and converted to the corresponding digital FBAS signal. This sampling is required for the following digital color decoder.

[0018] The free-running clock frequency f_(T2) is obtained by division from a similarly free-running high-frequency and quartz-coupled clock signal with a frequency of at least f₀=600 MHz. The high frequency f₀ ensures the phase resolution 1/f₀<3 ns required for 100 Hz television receivers. In this case, f₀=648 MHz.

[0019] In this case, the free-running clock frequency is f_(T2=)20.25 MHz. A divider 11 is provided which simply monitors the state change of the most significant bit (MSB), that is, of bit no. 5, of the data words generated by a 5-bit counter 9 operated at the high-frequency clock frequency f₀, and corresponding to the respective count, and output as clock frequency f_(T2) through a register 12 also operated at f₀. In this way, the free-running clock signal f_(T2)=f₀/2⁵=f₀/32=20.25 MHz is generated.

[0020] In a digital 100 Hz television receiver, the image must be displayed line-coupled at 36 MHz at the output after a corresponding 100 Hz conversion. To generate this line-coupled clock frequency f_(T1), a digital phase-locked loop is used together with a digital phase detector and loop filter 7, and a digitally controlled oscillator 8, in combination with an interpolator 6. Digital phase detector and loop filter 7 is operated at the coupled clock frequency f_(T1) and determines the phase deviation between the horizontal sync pulses contained in the FBAS signal and the clock signals momentarily generated by digitally controlled oscillator 8 which are output as the coupled clock signal f_(T1). The phase deviation is converted to an incremental value INCR for digitally controlled oscillator 8 operated at the high clock frequency f₀ so that in the adjusted state of digitally controlled oscillator 8 an output frequency f_(T1) is generated which is matched to the horizontal frequency of the FBAS signal and coupled to it.

[0021] Based on the fixed connection between the free-running clock frequency f_(T2) and the coupled clock frequency f_(T1) via the high-frequency quartz clock frequency f₀, the phase position between these two clock frequencies may easily be tracked with a resolution of 1/f₀.

[0022] The count of 5-bit counter 9 provides the momentary phase of free-running clock frequency f_(T2) (20.25 MHz). If the momentary count of counter 9 is stored with each active clock-pulse edge of coupled clock frequency f_(T1) (36 MHz) in a register 10, this stored value may be used directly to convert the 20.25 MHz sampling values to the corresponding 36 MHz sampling values, since each value stored in register 10 is a measure of the phase deviation between the coupled clock signal f_(T1) (36 MHz) and the free-running clock signal f_(T2) (20.25 MHz).

[0023] For this purpose, interpolator 6 is provided, already mentioned and operated at the coupled clock frequency f_(T1), to which the respective count stored in register 10 is fed. In the embodiment shown, interpolator 6 performs a linear interpolation which is sufficient for the considered case of sync recognition. The measurement of two sampling values of the digital FBAS signal provided by analog-to-digital converter 1 at free-running clock frequency f_(T2)=20.25 MHz is sufficient for the linear interpolation. For this reason, two registers 2 and 3 operated at free-running clock frequency f_(T2) follow analog-to-digital converter 1, which registers store two successive sampling values for the digital FBAS signal. In order to provide these sampling values to interpolator 6, the sampling values must be stored simultaneously along with the phase value stored in register 10. This task is performed by two registers 4 and 5 operated at the coupled clock frequency f_(T1) in which one sampling value each is thus stored from the 20.25 MHz system synchronously with register 10.

[0024] In the event interpolator 6 is to be used to perform not just a linear interpolation but a more-significant interpolation which requires more than two sampling values of the digital FBAS signal, the number of registers operated at the free-running clock frequency f_(T2), as well as the number of registers operated at the coupled clock frequency f_(T1), must be increased.

[0025] Based on the interpolation of the FBAS signal sampled at free-running frequency f_(T2), interpolator 6 determines new digital sampling values for the coupled clock frequency f_(T1). The digital FBAS data stream thus obtained at frequency f_(T1) then serves as the input signal for the digital phase-locked loop, with the result that the line-coupled clock frequency f_(T1) is finally generated by digitally controlled oscillator 8 which may be in the form of a closed-loop-controlled adder. 

1. Method for generating a clock signal coupled to a reference signal, comprising the steps: a) supply of an operating clock signal (f₀) b) supply of a first clock signal (f_(T2)), c) supply of a sequence of sampling values of the reference signal (FBAS) at the frequency of the first clock signal (f_(T2)), d) supply of a second clock signal (f_(T1)), e) determination of the phase deviation between the first clock signal (f_(T2)) and the second clock signal (f_(T1)), and f) conversion of the sampling values of the reference signal (FBAS) with the frequency of the first clock signal (f_(T2)) to corresponding sampling values with the frequency of the second clock signal (f_(T1)), said conversion being based on the phase deviation determined in step e), wherein the resulting sampling values of the reference signal (FBAS) are used in step d) as the target specification to generate the second clock signal (f_(T1)) in order to thereby generate the second clock signal (f_(T1)) coupled with the reference signal (FBAS).
 2. Method according to claim 1, in which the first clock signal (f_(T2)) and/or the second clock signal (f_(T1)) is generated from the operating clock signal.
 3. Method according to claim 1, characterized in that the reference signal (FBAS) is coupled to the first clock signal (f_(T2)) or the second clock signal (f_(T1)), and the first clock signal (f_(T2)) or the second clock signal (f_(T1)) is generated from the reference signal (FBAS).
 4. Method according to claim 1, characterized in that the first clock signal (f_(T2)) and/or the second clock signal (f_(T1)) is generated from an externally supplied clock signal.
 5. Method according to one of claims 1 through 4, in which the sampling values are generated as digitized sampling values.
 6. Method according to one of the foregoing claims, characterized in that in step f) an interpolation is performed on the sampling values, provided in step c), of the reference signal (FBAS) at the frequency of the first clock signal (f_(T2)), and on the basis of the phase deviation determined in step e), wherein the interpolated digitized sampling values of the reference signal (FBAS) thus obtained are used in step d) as the target specification to generate the second clock signal (f_(T1)).
 7. Method according to one of the foregoing claims, characterized in that a linear interpolation is performed in step f).
 8. Method according to one of the foregoing claims, characterized in that the second clock signal (f_(T1)) is generated in step d) with the aid of a digital phase-locked loop (7, 8).
 9. Method according to one of the foregoing claims, characterized in that a high-frequency quartz-coupled clock signal is used as the operating clock signal (f₀).
 10. Method according to one of the foregoing claims, characterized in that the sampling values of the reference signal (FBAS) supplied in step c) are temporarily stored at the frequency of the second clock signal (f_(T1)) before their use in the conversion effected in step f), and are subsequently used only for the conversion.
 11. Method according to claim 10, characterized in that in step e) the phase deviation between the first clock signal (f_(T2)) and the second clock signal (f_(T1)) is determined at the frequency of the second clock signal (f_(T1)), and temporarily stored synchronously with the digitized sampling values of the reference signal (FBAS).
 12. Method according to one of the foregoing claims, characterized in that in step b) the first clock signal (f_(T2)) is generated by evaluating the count of a counter (9) operated with the operating clock signal (f₀).
 13. Method according to claim 12, characterized in that the momentary count of the counter (9) is determined at the frequency of the second clock signal (f_(T1)), and the count determined each time is used in step e) as the measure of the phase deviation between the first clock signal (f_(T2)) and the second clock signal (f_(T1)).
 14. Device for generating a clock signal coupled to a reference signal, comprising: a first clock-signal generating device (11) to generate a first clock signal (f_(T2)), a device operated with the first clock signal (f_(T2)) which obtains a sequence of sampling values for the reference signal (FBAS), a second clock-signal generating device (7, 8) to generate a second clock signal (f_(T1)), a phase-deviation determination device (10) to determine the phase deviation between the first clock signal (f_(T2)) and the second clock signal (f_(T1)), and a conversion device (6) to convert the sampling values of the reference signal (FBAS) with the frequency of the first clock signal (f_(T2)) from device (1) to the corresponding sampling values with the frequency of the second clock signal (f_(T1)), said conversion being based on the phase deviation determined by the phase-deviation determination device (10), wherein the sampling values of the reference signal (FBAS) output by the conversion device (6) are supplied to the second clock-signal generating device (7, 8) as the target specification for generating the second clock signal (f_(T1)), so that the second clock signal (f_(T1)) is output by the second clock-signal generating device (7, 8) coupled to the reference signal (FBAS).
 15. Device according to claim 14, characterized in that the first clock-signal generating device (11) generates the first clock signal (f_(T2)) and/or the second clock signal (f_(T1)) from the operating clock signal (f₀).
 16. Device according to claim 14, characterized in that the first clock-signal generating device (11) generates the first clock signal (f_(T2)) or the second clock signal (f_(T1)) from the reference signal (FBAS).
 17. Device according to claim 14, characterized in that the first clock-signal generating device (11) generates the first clock signal (f_(T2)) and/or the second clock signal (f_(T1)) from an externally supplied clock signal which specifically corresponds to the first clock signal (f_(T2)).
 18. Device according to claim 14, in which the device (1) is an analog-to-digital converter.
 19. Device according to one of the foregoing claims, in which the conversion device (6) outputs digitized sampling values.
 20. Device according to one of the foregoing claims, characterized in that the conversion device (6) is designed to perform the function of an interpolator, specifically a linear interpolator.
 21. Device according to one of the foregoing claims, characterized in that the second clock-signal generating device (7, 8) is designed in the form of a digital phase-locked loop which includes a digital phase detector device (7) and a digitally controlled oscillator device (8), wherein the digitally controlled oscillator device (8) generates the second clock signal (f_(T1)), and wherein the digital phase detector device (7) determines the phase deviation between the digitized sampling values of the reference signal (FBAS) output by the conversion device (6) and the second clock signal (f_(T1)) generated by the digitally controlled oscillator device (8) and, depending thereon, generates a digital incremental value (INCR) for the digitally controlled oscillator device (8) by which to adjust the frequency of the second clock signal (f_(T1)).
 22. Device according to one of the foregoing claims, characterized in that the operating clock signal (f₀) is a high-frequency quartz-coupled clock signal.
 23. Device according to one of the foregoing claims, characterized in that first memory means (2, 3) are provided for temporarily storing the sampling values of the reference signal (FBAS) with the frequency of the second clock signal (f_(T1)) output by the analog-to-digital converter (1), and that second memory means (4, 5) are provided to temporarily store the digital sampling values with the frequency of the first clock signal (f_(T2)) temporarily stored in the first memory means (2, 3), and to feed said sampling values to the conversion device (6).
 24. Device according to one of the foregoing claims, characterized in that a counter (9) operated at the operating clock frequency (f₀) is provided, and that the first clock-signal generating device (11) is designed so that the first clock signal (f_(T2)) is generated by evaluating the count of the counter (9).
 25. Device according to claim 24, characterized in that the phase-deviation determination device includes memory means (10) to determine the momentary count of the counter (9) at the frequency of the second clock signal (f_(T1)), and to feed the count determined each time to the conversion device (6) as the measure of the phase deviation between the first clock signal (f_(T2)) and the second clock signal (f_(T1)).
 26. Device according to one of the foregoing claims, characterized in that the reference signal (FBAS) is a video signal, specifically a television signal, and that the frequency (f₀) of the operating clock signal, from which the first and/or second clock signal (f_(T2); f_(T1)) is derived, is at least 600 MHz. 